About this Course
4.5
153 ratings
41 reviews
100% online

100% online

Start instantly and learn at your own schedule.
Flexible deadlines

Flexible deadlines

Reset deadlines in accordance to your schedule.
Intermediate Level

Intermediate Level

Hours to complete

Approx. 29 hours to complete

Suggested: 6 hours/week...
Available languages

English

Subtitles: English

Skills you will gain

Primality TestVerilogDigital DesignStatic Timing Analysis
100% online

100% online

Start instantly and learn at your own schedule.
Flexible deadlines

Flexible deadlines

Reset deadlines in accordance to your schedule.
Intermediate Level

Intermediate Level

Hours to complete

Approx. 29 hours to complete

Suggested: 6 hours/week...
Available languages

English

Subtitles: English

Syllabus - What you will learn from this course

Week
1
Hours to complete
5 hours to complete

What's this programmable logic stuff anyway? History and Architecture

What's this programmable logic stuff anyway? In Module 1 you learn about the history and architecture of programmable logic devices including Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC, recite the historical development of programmable logic devices; and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs....
Reading
9 videos (Total 46 min), 4 readings, 2 quizzes
Video9 videos
Course Overview6m
1. Welcome to the world of programmable logic and FPGA design1m
2. A Brief History of Programmable Logic9m
3. CPLD Architecture5m
4. LUTs and FPGA Architecture8m
5. LUTs for Logic Design2m
6. Designing Adders6m
7. Designing Multipliers3m
Reading4 readings
About This Course10m
Hardware Requirements10m
Week 1 Suggested Readings20m
Release of Week 2 Files10m
Quiz1 practice exercise
Mission 002: Week 1 Quiz34m
Week
2
Hours to complete
5 hours to complete

FPGA Design Tool Flow; An Example Design

In Module 2 you will install and use sophisticated FPGA design tools to create an example design. You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier, and how to verify the integrity of the design using the RTL Viewer and by simulation using ModelSim. Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure....
Reading
11 videos (Total 121 min), 1 reading, 3 quizzes
Video11 videos
2. Downloading Quartus Prime2m
3. Installing Quartus Prime2m
4. Introducing Quartus Prime11m
5. Create a design project in Quartus Prime7m
6. Create a design in Quartus Prime13m
7. Compile a Design17m
8. View the RTL16m
9. Timing Analysis with Time Quest I9m
10. Timing Analysis with Time Quest II16m
11. Simulate a design with ModelSim17m
Reading1 reading
Week 2 Suggested Readings20m
Quiz2 practice exercises
Mission 003 : Practice Opportunity30m
Mission 005: Week 2 Quiz38m
Week
3
Hours to complete
4 hours to complete

FPGA Architectures: SRAM, FLASH, and Anti-fuse

FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs. ...
Reading
8 videos (Total 80 min), 2 readings, 1 quiz
Video8 videos
2. Xilinx CPLD Architecture7m
3. Xilinx Small FPGAs8m
4. Xilinx Large FPGAs11m
5. Altera CPLDs and Small FPGAs8m
6. Altera Large FPGAs9m
7. Microsemi Single-chip FPGA solutions14m
8. Lattice Single-Chip FPGA solutions14m
Reading2 readings
Week 3 Suggested Readings20m
Release of Week 4 Files10m
Quiz1 practice exercise
Mission 006: Week 3 Quiz32m
Week
4
Hours to complete
7 hours to complete

Programmable logic design using schematic entry design tools

In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs. ...
Reading
10 videos (Total 180 min), 1 reading, 2 quizzes
Video10 videos
2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy26m
3. Improving Productivity with IP Blocks25m
4. Improving Timing with Pipelining18m
5. FPGA IO: Getting In and Getting Out8m
6. Pin Assignments: Making them Spot On!20m
7. Programming the FPGA10m
8. Becoming one with Q: Qsys System Design20m
9.a Becoming one with Q Part II: Qsys System Design Finishing Touches25m
9.b Becoming one with Q Part III: Qsys System Design Finishing Touches19m
Reading1 reading
Week 4 Suggested Readings10m
Quiz1 practice exercise
Mission 008: Week 4 Quiz32m
4.5
41 ReviewsChevron Right

Top Reviews

By SUSep 18th 2018

Very challenging course with tough assignments and quizes to pass with deadlines but i enjoyed this.\n\nI got practical experience in designing, compiling and analyzing FPGA circuits.

By FCMay 7th 2018

This course will take you from a very basic understanding of FPGA technology to experiencing most facets of the design process. I would like to see more courses on this topic.

Instructor

Avatar

Timothy Scherr

Senior Instructor and Professor of Engineering Practice
Electrical, Computer, and Energy Engineering

About University of Colorado Boulder

CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies....

Frequently Asked Questions

  • Once you enroll for a Certificate, you’ll have access to all videos, quizzes, and programming assignments (if applicable). Peer review assignments can only be submitted and reviewed once your session has begun. If you choose to explore the course without purchasing, you may not be able to access certain assignments.

  • When you purchase a Certificate you get access to all course materials, including graded assignments. Upon completing the course, your electronic Certificate will be added to your Accomplishments page - from there, you can print your Certificate or add it to your LinkedIn profile. If you only want to read and view the course content, you can audit the course for free.

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