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In this first lesson, we're going to see

what are the basic components of sequential circuits.

We already know that a fundamental property of sequential

systems is their ability to store data.

So, the basic component is one able to store one bit.

Generic names are bistable, a circuit with

two stable states, or simply memory element.

An easy way to implement a memory element that can store one bit is this one:

two interconnected inverters.

If at some time the output of this inverter is equal to 0,

then the output of the second one will be equal to 1,

and once again the output of this one will be equal to 0.

So, this is a stable state, but there is another stable state if in some

moment the output of this inverter is equal to 1; then its output will be

equal to 0, and again the output of this one will be equal to 1.

So, this is a circuit with two stable states.

It remains to define a way to externally control the state of this

memory element. For that, we add to the circuit two

(this one and this one) two 3-state buffers, one controlled by the input

signal "load" and the other one controlled by the input signal

load but inverted. If load is equal to zero, then the circuit is equivalent

to the following: the input D and a 3-state buffer, but

with load equal to 0, so that it's an open circuit,

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number 2,

and a connection through this 3-state buffer

controlled by load inverted, so that this connection exists.

So that a bit, some bit, is stored within this circuit.

This will be the output NOT Q, and this will be the output Q.

If load is equal to 1, then the equivalent circuit is this one.

D, then, as load is equal to 1,

D is transmitted to this point

and it's the input of inverter number one.

Here is inverter number two.

But in this case, as load is equal to 1,

then this 3-state buffer is in high impedance state,

so that there is no connection

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and this is its symbol.

This table define its behavior:

when load is equal to 1, then the next value of Q is

equal to the current value of input D,

and when load is equal to 0, then the next

value of Q is equal to the latest value of Q,

the circuit doesn't change it's internal state.

The corresponding equation, when load is equal to 1 is this one:

next_Q equal to the value of D.

There are other bistable components in which the control

of the stable state is performed in a different way.

Examples are given in this table.

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The combination S and R equal to 1 is not allowed,

and when both are equal to zero the bistable doesn't change its state.

JK bistable are similar.

In this case, S is replaced by J and R replaced by K.

The difference is that the combination J equal to K

equal to 1 is allowed and in this case the next value

of Q will be the inverse of the current value of Q,

so that the circuit state will change from 1 to 0, or from 0 to 1.

You can see that the circuit equation is Q (next_Q) equal

to NOT(Q) when J and K are both equal to 1.

Finally, T flip-flop (or T bistable) is the same as a

JK bistable with J equal to K equal to T,

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so that when T is equal to 1, then the next state

of Q is the inverse of the current state of Q.

Nevertheless, the most used type of bistable is

D-type, that we have already analyzed before.

There are two types of type-D bistables called Latches and Flip-Flops.

In the case of a latch, it's what

we've seen before with the pair of interconnected inverters:

the state can change at any time when

the synchronization input signal is equal to 1.

This was the symbol.

In the case of a Flip-Flop, and this is the symbol, the

state can only change on a positive edge (a positive edge

means a transition from 0 to 1) of the synchronization signal,

or also on a negative edge (from 1 to 0).

In the case of a positive edge, the symbol is this one.

In the case of a negative edge, a small circle should be added

on the load input. Let us see an example.

First consider a latch with these input signals.

When the input signal load is equal to 1,

then the latch is in the transparent state,

and as we can see, the value of the output, here

and here is exactly the same as the value of the input,

and when Load is equal to 0, then it remains in the same state as just before.

Now, in the case of a flip flop, what is determining is not the value of load,

but the active transitions, in this case from 0 to 1,

active transitions of the load signal.

The value of input D is sampled by the positive edges of

load, and the result is this one; so, here the value 1

is sampled, here too, and here the value 0 is sampled.

An example: this transition here

is not transmitted to the output, while in the case of the latch it was.

Or this pulse is not transmitted to the output while in the case of the latch

it was. The only moment when the output can change its state

is when there is positive latch of the load signal. Now a quizz.

Sometimes, memory elements have additional asynchronous control inputs,

that is to say, inputs that can modify the bistable state,

the component state, independently of the synchronization input.

An asynchronous input RESET will make the state equal to 0,

and an asynchronous input RESET will make the state equal to 1.

This is the symbol of a flip flop with SET and RESET control inputs.

And let us see an example.

When RESET is equal to 1, then Q will be equal

to 0, independently of the synchronization signal CK.

And, the same, when SET is equal to one, then Q will go from 0 to 1.

We have already seen several examples of time diagrams.

They describe the circuit behavior in function of the time.

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And I propose you an exercise.

Try to complete the time diagram

corresponding to this circuit

with these values of the input signals.

The equations of the circuit are the following ones.

This is flip-flop number 0 and this is flip-flop number 1; then we can see that

Q0, the next value of Q0, is equal to the NAND of x and Q0;

and the next state of Q1 is equal

to the OR function of Q0 and Q1 inverted.

So that when x is equal to 1, the next value of Q0 is the inverse of Q0;

when x is equal to 0, the next value of Q0 is 1; as regards Q1,

when Q0 is equal to 0, the next value of Q1 is NOT(Q1),

and when Q0 is equal to 1, then the next value of Q1 is 1.

A first point: initially we don't know the value of Q0 and Q1,

so that we don't know which will be their next value,

and we don't know which is the value of Y.

So, we must wait for a RESET pulse to know the initial value of Q0 and Q1.

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With this reset pulse, at both flip-flop 0 and flip-flop 1,

the value of Q0 will be equal to 0, and the same for the value of Y.

Then we have just to use the equation: when there is a first positive edge,

as X is equal to 1, we know that the next value of Q0 is NOT(Q0),

so Q0 goes from 0 to 1. As the value of Q0,

just before, was 0,

then the next value of Q1 will be NOT(Q1),

so that Q1 goes from 0 to 1.

With the next positive edge, X is still equal to 1, so

that Q0 will change its state once again, and goes from 1 to 0.

But just before the state of Q0 was 1, and when Q0 is 1

the next state of Q1 is 1. So, Q1 remains equal to 1.

Finally, when we input the third positive edge

on CK, now X is equal to 0 so that the next value

of Q0 is 1 and, as just before Q0 was

equal to 0, then the next value of Q1 is NOT(Q1).

Finally, we must compute the value of Y and

you can see that Y is the product

of Q0 and Q1.

So, Y is the product of Q0 and Q1.

Here, it's equal to 1,

here to 0,

and here it remains equal to 0.

Summary.

In this lesson we have introduced the concept of

bistable component and specially of type-D bistable component.

We have seen the difference between latches

and flip-flops and have given examples of time diagrams.

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