Conversely, if the voltage here was larger than x,

the difference would be negative and this would drive the output down.

So the only equilibrium point for

the system is when the voltage at the inverting input is exactly equal to x,

which of course means that the output voltage is equal to x as well.

So the input-output relationship of the closed loop is output equal to the input.

This configuration is known as a buffer stage,

because although the output has the same voltage as the input, the second property

of the ideal op-amp prevents any current from flowing into the amplifier.

And therefore there is a separation between this side and

that side of the amplifier.

This is very useful for

taking measurements without perturbing the measured quantity.

We can complexify the closed loop a little bit by adding a couple of resistors.

In this case we have what is called an inverting amplifier.

This is only slightly more complex than the simple closed loop we saw before.

Again, the system will stabilize when the difference between inverting and

non-inverting inputs is zero.

So we can say that voltage here, let's call it V0 is equal to 0

because the non-inverting input is connected to ground.

That means that the current flow-in in the first resistor will be according to Ohm's

law, i0 = x/R1.

This current will not be able to flow into the operational amplifier

because of the second law, so it'll have to flow into this resistor here.

And therefore the output voltage will be just

the voltage's drop over R2 caused by i0.

And so y = -R2/i0, which gives us the final

input-output relationship for the inverting amplifier.

The output is a fraction of the input with a change of sign.

We're now ready to look at an A/D converter.

The device starts with the sample and hold circuit that performs the sampling.

So we have our analogue input here.

Here we have an op-amp in buffer configuration and

here we have a mosfet which is really like a switch.

And here we have a train of pulses at the sampling frequency.

When a pulse reaches the gate at the mosfet,

the mosfet closes very briefly and allows the first buffer

to charge this capacitor to the instantaneous level of the input signal.

The capacitor is connected to another buffer stage that will put out the value

measured by the capacitor for the duration of the interval between pulses.

We put a buffer stage here so that we can put out a constant voltage

without discharging the capacitor between sample and instance.

An analog-to-digital converter needs not only to sample the input signal, but

also to quantize it.

So the sample on hold provides a stable voltage level between sampling times and

now we need a circuit that converts that to binary format.

Here we have a simple diagram of a 2-Bit quantizer.

What this quantizer does is take a maximum positive voltage V0 and

a minimum negative voltage -V0, this could be the A and

B extrema that we used in our quantization example.

And then it uses a series of four resistors of equal value

to produce intermediate boundary levels, the iKs

in our quantization example, that will be used to define the quantization regions.

Here you have +0.5 volts, you have 0 volts, you have -0.5 volts.

So we're dividing the interval from V0 to -V0 into four equally spaced intervals.

These reference voltages here are used with the bank of competitors,

so operational amplifiers in open loop to determine which

quantization interval the current sample value belongs to.

So let's work out an example with an input voltage of 0.2 V0.

So what we have here is that the first comparator will have

0.2 volts at the non-inverting input with the reference of 0.05 volts.

So the reference is higher, so here the out put will be a negative voltage

This competitor will compare 0.2 volts to 0 volts.

And so, this competitor will output a positive voltage, and similarly,

this one will compare 0.2 to -0.5, so again, the output will be positive.

Next we have a logic network that will encode

this comparison levels into a binary value.

These are exclusive or gates and the truth table for these gates is the following.