Partial Reconfiguration Design Flows

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From the course by Politecnico di Milano

FPGA computing systems: Background knowledge and introductory materials

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Politecnico di Milano

FPGA computing systems: Background knowledge and introductory materials

22 ratings

This course is for anyone passionate in learning how a hardware component can be adapted at runtime to better respond to users/environment needs. This adaptation can be provided by the designers, or it can be an embedded characteristic of the system itself. These runtime adaptable systems will be implemented by using FPGA technologies. Within this course we are going to provide a basic understanding on how the FPGAs are working and of the rationale behind the choice of them to implement a desired system. This course aims to teach everyone the basics of FPGA-based reconfigurable computing systems. We cover the basics of how to decide whether or not to use an FPGA and, if this technology will be proven to be the right choice, how to program it. This is an introductory course meant to guide you through the FPGA world to make you more conscious on the reasons why you may be willing to work with them and in trying to provide you the sense of the work you have to do to be able to gain the advantages you are looking for by using these technologies. We rely on some extra readings to provide more information on the topic covered in this course. Please NOTE that most of the time, these documents are provided through the IEEE Xplore Digital Library, which means that, to access them, you have to have a valid IEEE subscriptions, either does by yourself or through your university/company. The course has no prerequisites and avoids all but the simplest mathematics and it presents technical topics by using analogizes to help also a student without a technical background to get at least a basic understanding on how an FPGA works. One of the main objectives of this course is to try to democratize the understanding and the access to FPGAs technologies. FPGAs are a terrific example of a powerful technologies that can be used in different domains. Being able to bring this technologies to domain experts and showing them how they can improve their research because of FPGAs, can be seen as the ultimate objective of this course. Once a student completes this course, they will be ready to take more advanced FPGA courses.

From the lesson

Design Flows

After presenting different solutions proposed to design and implement dynamic reconfigurable systems, this module will describe a general and complete design methodology that can be followed as a guideline for designing reconfigurable computing systems. To design and implement a reconfigurable computing system, designers need Computer-Aided Design (CAD) tools for system design and implementation, such as a design analysis tool for architecture design, a synthesis tool for hardware construction, a simulator for hardware behavior simulation, and a placement and routing tool for circuit layout. We may build these tools ourselves or we can also use commercial tools and platforms for reconfigurable system design. The first choice implies a considerable investment in terms of both time and effort to build a specific and optimized solution for the given problem, while the second one allows the re-use of knowledge, cores, and software to reach a good solution to the same problem more rapidly. This module is guiding the students through an historical view on how CAD frameworks evolved through the years. This is done to show how fast the technology is evolving and the rationale behind the choice made to improve the users experience when working with an FPGA-based system. Not only commercial tools are described, but also the personal journey done by the course instructor and his research team, starting from his early days as a PhD up to the research challenges they are nowadays working on.

Partial Reconfiguration Design Flows4:58

Xilinx Difference Based Partial Reconfiguration5:23

Xilinx Module Based Partial Reconfiguration5:02

Xilinx Partial Reconfiguration (PR) Flow5:33

Moudle Based vs Partial Reconfiguration Design Flows17:14

Meet the Instructors

Marco Domenico Santambrogio
Associate Professor
DEIB - Dept. of Electronics, Information and Bioengineering

Hi!

Welcome back to our example where we have been able to configure our FPGA with a given design!

Even if you are not familiar with it, well, this is not a big issue, the basic idea is

that we went through the entire design process and we have been able to create the proper

configuration bitstream.

This is great, we have a working FPGA, and this is what we are here for!

But wait…

What?

Wait a second Something is happening…

While we were executing our design we just realised that something has to be changed…

It is not a big thing, we just have to modify the configuration of one CLB.

Umh… not a big thing?

Are you sure?

Well, you are right, it is not a big thing… it is HUGE! GIGANTIC!

We don’t know how to do it!

This means that even if the update is small, even if it is not involving the other elements

we do have to start from scratch the entire design process.

Wow… that seems to be insane!

It’s ok with us, we are just using a super simple FPGA, but what if we are going to work with a real one?

Well, this can be HUGE! and this is exactly the rationale behind

the PARTIAL RECONFIGURATION!

We do need to work towards the creation of a RECONFIGURABLE-FRIENDLY ECOSYSTEM!

RECONFIGURABLE SYSTEMS are gathering an increasing interest

from both the scientific and the industrial world.

The need of a comprehensive framework which can guide designers

through the whole implementation process is becoming stronger.

It is quite hard to have just in one framework support to:

. define which IP-Core has to become a reconfigurable core

. perform the actual swap of reconfigurable cores and the FPGA reconfiguration

. define interconnections among reconfigurable cores

. identify from an high-level or RT-Level specification how to define reconfigurable cores

And these are just few examples, I can provide you more.

Because of this scenario we can find many examples of tools/initiatives to try to cope with it.

One of the earliest examples in trying to provide a tool

to design partial configuration bitstream has been done by Xilinx.

They have been working on a design flow for partially reconfigurable architectures

which was characterised by a set of subsequent phases to implement the architecture

where PARTIALLY RECONFIGURABLE REQUIREMENTS were explicitly exposed.

In having a look to the history of Xilinx efforts in providing tools to support

partial reconfiguration we can identify three official design flows:

. DIFFERENCE BASED, also known as SMALLBIT MANIPULATION

. MODULE BASED

. PR, that was the shorten version of PARTIAL RECONFIGURATION

And nowadays, PR is fully integrated into Xilinx tool flows.

Xilinx has been always interested in innovating and in trying to provide to the designers

tools capable to answer to theirs needs.

Over the last two decades they’ve been able to reinvent their tools quite well.

They started with ISE and was basically a framework to create configuration bitstream

starting from a VHDL/Verilog description.

Xilinx realised that designers were looking for something more, something different.

They saw an opportunity in opening the FPGA world to people not fully trained in VHDL

and Verilog… and that is when EDK and SDK arrived on the market.

These tools were providing building blocks to the designer to allow him/her to assemble them

to create a working system.

One of the interesting part was that, if you were able to design your own IP in VHLD/Verilog

you were still having the opportunity of integrating it into a design that was created in a much easier way.

This means that, even if you were a skilled IP designer, you were gaining in productivity

because Xilinx was providing you a tool to design the overall system

where to embed/add your IP without having to worry of the entire system design by yourself.

The next bit step was the introduction of the support to the High Level Synthesis.

And this was done with Vivado HLS but this was not enough.

Xilinx was looking for more.

They were looking for tools to allow both an embedded system designer and an HPC one

to have the same design experience, or at least to gain the same benefits

in terms of productivity… and this is where we are now, with SDSoC and SDAccel.

Obviously there are other tools, I just named few examples to give you an idea

on how things have changed and companies were not the only one in following this race.

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