2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop

Loading...
From the course by University of Illinois at Urbana-Champaign
VLSI CAD Part I: Logic
75 ratings
University of Illinois at Urbana-Champaign
75 ratings
From the lesson
2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
In Week 3, we will move from "representing" things to "synthesizing" things. In this case, synthesis means "optimization", or maybe the word "minimization" is more familiar from hand work with Kmaps or Boolean algebra.

Meet the Instructors

  • Rob A. Rutenbar
    Rob A. Rutenbar
    Adjunct Professor
    Department of Computer Science

Explore our Catalog

Join for free and get personalized recommendations, updates and offers.